SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 57

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.3.9
12.3.10
6289D–ATARM–3-Oct-11
New ARM Instruction Set
Thumb Instruction Set Overview
.
Table 12-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Table 5 shows the Thumb instruction set.
Table 12-4.
Mnemonic
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
SMULWy
SMLAWy
SMLAxy
SMULxy
QDADD
QDSUB
SMLAL
BLX
QADD
QSUB
BXJ
(1)
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
Operation
Move
Add
Subtract
Compare
Test
Logical AND
New ARM Instruction Mnemonic List
Thumb Instruction Mnemonic List
Operation
Branch and exchange to
Java
Branch, Link and exchange
Signed Multiply Accumulate
16 * 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate
32 * 16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with
double
Table 12-4
Mnemonic
MVN
ADC
SBC
CMN
NEG
BIC
Mnemonic
MRRC
MCRR
MCR2
CDP2
BKPT
STRD
LDRD
STC2
LDC2
PLD
CLZ
gives the Thumb instruction mnemonic list.
AT91SAM9R64/RL64
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
Operation
Move double from
coprocessor
Alternative move of ARM reg
to coprocessor
Move double to coprocessor
Alternative Coprocessor
Data Processing
Breakpoint
Soft Preload, Memory
prepare to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Coprocessor
Count Leading Zeroes
Alternative Load to
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