SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 446

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 34-3. Baud Rate Generator
34.6.1.1
Table 34-2.
6289D–ATARM–3-Oct-11
Source Clock
Baud Rate Calculation Example
3 686 400
4 915 200
5 000 000
7 372 800
MHz
Baud Rate in Asynchronous Mode
SCK
Baud Rate Example (OVER = 0)
Reserved
MCK/DIV
MCK
Expected Baud
If the external SCK clock is selected, the duration of the low and high levels of the signal pro-
vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the
signal provided on SCK must be at least 4.5 times lower than MCK.
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possi-
ble clock and that OVER is programmed at 1.
Table 34-2
clock frequencies. This table also shows the actual resulting baud rate and the error.
USCLKS
0
1
2
3
38 400
38 400
38 400
38 400
Rate
Bit/s
Baudrate
shows calculations of CD to obtain a baud rate at 38400 bauds for different source
16-bit Counter
=
Calculation Result
--------------------------------------------
(
8 2 Over
SelectedClock
CD
(
–
12.00
6.00
8.00
8.14
USCLKS = 3
)CD
0
SYNC
)
CD
>1
1
0
CD
12
6
8
8
1
0
OVER
Sampling
Divider
Actual Baud Rate
AT91SAM9R64/RL64
FIDI
38 400.00
38 400.00
39 062.50
38 400.00
Bit/s
0
1
SYNC
SCK
Baud Rate
Sampling
Clock
Clock
0.00%
0.00%
1.70%
0.00%
Error
446