SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 708

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.5
40.5.1
40.5.2
40.5.3
708
Product Dependencies
AT91SAM9R64/RL64
I/O Lines
Power Management
Interrupt
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the AC‘97 Controller receiver, the PIO controller must be configured in order for the
AC97C receiver I/O lines to be in AC‘97 Controller peripheral mode.
Before using the AC‘97 Controller transmitter, the PIO controller must be configured in order for
the AC97C transmitter I/O lines to be in AC‘97 Controller peripheral mode.
The AC‘97 Controller is not continuously clocked. Its interface may be clocked through the
Power Management Controller (PMC), therefore the programmer must first configure the PMC
to enable the AC’97 Controller clock.
The AC’97 Controller has two clock domains. The first one is supplied by PMC and is equal to
MCK. The second one is AC97CK which is sent by the AC97 Codec (Bit clock).
Signals that cross the two clock domains are re-synchronized. MCK clock frequency must be
higher than the AC97CK (Bit Clock) clock frequency.
The AC’97 Controller interface has an interrupt line connected to the Advanced Interrupt Con-
troller (AIC). Handling interrupts requires programming the AIC before configuring the AC97C.
All AC’97 Controller interrupts can be enabled/disabled by writing to the AC’97 Controller Inter-
rupt Enable/Disable Registers. Each pending and unmasked AC’97 Controller interrupt will
assert the interrupt line. The AC’97 Controller interrupt service routine can get the interrupt
source in two steps:
• Reading and ANDing AC’97 Controller Interrupt Mask Register (AC97C_IMR) and AC’97
• Reading AC’97 Controller Channel x Status Register (AC97C_CxSR).
Controller Status Register (AC97C_SR).
6289D–ATARM–3-Oct-11