SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 659

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6289D–ATARM–3-Oct-11
Table 39-8.
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7
and 6/7). The dithering pattern for the first pair member is the inversion of the one for the
second.
The DP_i registers contain a series of 4-bit patterns. The (3-m)
pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be
turned on or off in the current frame. The operation is shown by the examples below.
Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3,
respectively. The four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register
used is DP3_5 =”1010 0101 1010 0101 1111”.
The output sequence obtained in the data output for monochrome mode is shown in
Table 39-9.
Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates
4*n+0, and 4*n+1. A color pixel is composed of three components: {R, G, B}. Pixel p0 will be dis-
played sending the color components {R0, G0, B0} to the display. Pixel p1 will be displayed
sending the color components {R1, G1, B1}. Suppose that the data read from memory and
mapped to the lookup tables corresponds to shade level 10 for the three color components of
Gray Level
8
7
6
5
4
3
2
1
0
Frame
Number
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
...
Dithering Duty Cycle
Dithering Algorithm for Monochrome Mode
Pattern
1010
0101
1010
0101
1111
1010
0101
1010
...
Duty Cycle
4/7
1/2
3/7
2/5
1/3
1/4
1/5
1/7
0
ON
OFF
ON
OFF
ON
ON
OFF
ON
...
Pixel a
Pixel b
OFF
ON
OFF
ON
ON
OFF
ON
OFF
...
AT91SAM9R64/RL64
th
bit of the pattern determines if a
Pattern Register
DP4_7
~DP1_2
~DP4_7
~DP3_5
~DP2_3
~DP3_4
~DP4_5
~DP6_7
-
Pixel c
ON
OFF
ON
OFF
ON
ON
OFF
ON
...
Pixel d
OFF
ON
OFF
ON
ON
OFF
ON
OFF
...
Table
39-9.
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