SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 832

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 43-4. Touch Screen Pen Detect
43.7
832
Conversion Results
AT91SAM9R64/RL64
X
Y
X
Y
M
M
P
P
Screen panel when the system is running at high speed. The debouncer length can be selected
by programming the field PENDBC in
The Touch Screen Pen Detect can be used to generate a TSADCC interrupt to wake up the sys-
tem or it can be programmed to trig a conversion, so that a position can be measured as soon as
a contact is detected if the TSADCC is programmed for an operating mode involving the Touch
Screen.
The Pen Detect generates two types of status, reported in the
Both bits are automatically cleared as soon as the Status Register TSADCC_SR is read, and
can generate an interrupt by writing accordingly the
When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and
stored in the
“TSADCC Last Converted Data
The channel EOC bit and the bit DRDY in the
PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and
DRDY can trigger an interrupt.
Reading one of the
sponding EOC bit.
Reading
sponding to the last converted channel.
• the bit PENCNT is set as soon as a current flows for a time over the debouncing time as
• the bit NOCNT is set as soon as no current flows for a time over the debouncing time as
defined by PENDBC and remains set until TSADCC_SR is read.
defined by PENDBC and remains set until TSADCC_SR is read.
“TSADCC Last Converted Data Register”
VDDANA
VDDANA
GND
GND
“TSADCC Channel Data Register x (x = 0..5)”
“TSADCC Channel Data Register x (x = 0..5)”
GND
Register”.
“TSADCC Mode
To the ADC
“TSADCC Status Register”
clears the DRDY bit and the EOC bit corre-
“TSADCC Interrupt Enable
Debouncer
PENDBC
Register”.
of the current channel and in the
“TSADCC Status
Pen Interrupt
registers clears the corre-
are both set. If the
6289D–ATARM–3-Oct-11
Register”.
Register”: