L64724 LSI Logic Corporation, L64724 Datasheet - Page 104

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3-74
TXED[7:0]
Serial_B
Serial_C[1:0] Serial Transmission Control Bit C
SPI_M[3:0]
Serial_A
L64724 Registers
Serial Transmission End Data
When the APR 61 register is written, the TXED[7:0] bits
are serialized and transmitted as the last serial data byte,
and a STOP condition is generated on the SDATA
(XCTR[0]) and SCLK (XCTR[1]) pins.
Serial Transmission Control Bit B
The Serial_B bit indicates whether the host
microprocessor or on-chip microcontroller controls the
XCTR[2:0] pins. When the bit is 1, the on-chip
microcontroller controls the XCTR[2:0] pins. When the bit
is 0, the host microprocessor controls the pins.
The Serial_C[1:0] bits control whether the data is
serialized with a serial 2-wire or 3-wire protocol. These
bits are used to serialize data, as shown in the table
below:
For more details, see Appendix C “Programming the
Serializer.”
SPI_M
The SPI_M[3:0] bits contain the value of the denominator
for the Viterbi Code rate.
Serial Transmission Control Bit A
The Serial_A bit indicates whether the output pins
XCTR_OUT[3:0] are to be controlled directly as
programmed in the Group 4 APR 55 register “External
Control Output Bits,” XCTR[3:0], or by the serializer
module with data from the TXSD, STXD, and TXED
registers. When the bit is 0 (the default), it indicates that
control is as dictated by XCTR[3:0].
Serial_C[1:0]
0
0
1
1
0
1
0
1
Selected Function
Serial 2-Wire Interface
3-wire interface, ENABLE HIGH for all
valid data
3-wire interface, ENABLE HIGH for
1 clock cycle at the start of data transfer
3-wire interface, ENABLE HIGH for
1 clock cycle at the end of data transfer
[7:0]
[6:5]
[4:1]
7
0