L64724 LSI Logic Corporation, L64724 Datasheet - Page 141

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

5.6.1 Clock Acquisition and Tracking Modes
The Clock Recovery Loop operates in two modes:
In both modes, the Clock Recovery Loop takes its input from the Timing
Error Detector (TED).
The internal digital loop filter determines the loop characteristics using
parameters CLK_MU_SEL, CLK_LAMBDA_SEL, and CLK_BIAS as well
as the gains of the Timing Error Detector and NCO modules.
The CLK_MU_SEL and CLK_LAMBDA_SEL parameters are computed
according to
Equation 5.1
Equation 5.2
Equation 5.3
Fs is the sampling frequency, Fb is the baud rate, and DF_RATIO is the
decimation filter downsampling ratio, which can be 1, 2, 4, 8, or 16.
Based on the intermediate values
Equation
computed in
normally 1.0. The natural frequency (
Equation 5.4
Timing Clock Recovery
K
T
L
a
Clock Acquisition
Tracking
tim
dtim
=
=
=
------ -
Fb
------------------------- -
K
1
=
5.5, the values for CLK_MU_SEL and CLK_LAMBDA_SEL are
dtim
------ -
Fb
Fs
0.0388
n
2
T
L
Equation
Equation 5.6
---------------------------- -
DF_RATIO
2
tim
Timing Loop Phase Detector Gain
Symbol Time
Oversampling Ratio
1
5.1,
and
Equation
Equation
a
5.2, and
and
n
) of the loop is in radians/sec.
5.7. The damping factor (
b
, given in
Equation
Equation 5.4
5.3.
and
is
5-9