L64724 LSI Logic Corporation, L64724 Datasheet - Page 38

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.3 Groups 0 and 1: Address Pointer Register
3-8
5. The L64724 is now in the acquisition mode. When data is applied at
For details on how reset affects the various register bits, see
3.10, “Reset Effect on Register Bits,” page
The Address Pointer Register (APR) is a 13-bit R/W register that points
to the registers in Groups 2, 3, and 4. It is accessed when A[2:0] = 0b000
and 0b001. Before accessing a register location from Group 2, 3, or 4,
you must initialize the APR contents with the address of the first register
entry that you are going to read or write. The APR automatically
increments after reading or writing a byte within a Group 2 (A[2:0] =
0b010), Group 3 (A[2:0] = 0b011) Group 4 (A[2:0] = 0b100) or Group 5
(A[2:0] = 0b101) register.
Two consecutive writes are required to load the complete APR. The first
write is to Group 0 to load the eight LSBs, the second to Group 1 to load
the five MSBs. The APR can be read as well as written.
Group 1, Data Bus D[7:0]
The reserved bits in these registers are for LSI internal test procedures
and future expansion and should always be set to zero.
L64724 Registers
7
12
Reserved
the L64724 input, it is ready to start demodulating and decoding.
5
4
APR[12:8]
Address Pointer, APR[12:0]
0
Group 0, Data Bus D[7:0]
7
3-82.
APR[7:0]
Section
0
0