L64724 LSI Logic Corporation, L64724 Datasheet - Page 42

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3-12
S2_LS_IE
S2_S_IE
S1_LS_IE
S1_S_IE
Reserved
The following register diagram shows the bit organization of SMR[15:8].
Descriptions of the bits follow the register diagram. The L64724 sets all
the bits in SMR[15:8] to 0 after a software or a hardware reset.
L64724 Registers
Stage 2 Loss of Synchronization Interrupt Enable
The microprocessor sets the S2_LS_IE bit to enable an
interrupt when Deinterleaver/Reed-Solomon Decoder
synchronization is lost.
Stage 2 Synchronization Interrupt Enable
The microprocessor sets the S2_S_IE bit to enable an
interrupt when Deinterleaver/Reed-Solomon Decoder
synchronization is established.
Stage 1 Loss of Synchronization Interrupt Enable
The microprocessor sets the S1_LS_IE bit to enable an
interrupt when Viterbi Decoder synchronization is
lost.
Stage 1 Synchronization Interrupt Enable
The microprocessor sets S1_S_IE to enable an interrupt
when Viterbi Decoder synchronization is established.
Reserved
The Reserved bit is for LSI Logic internal use only and
should always be cleared to 0.
S2_LS_IE
S1_LS_IE
S2_S_IE
S1_S_IE
0
1
0
1
0
1
0
1
Definition
Disable Stage 2 Synchronization Interrupt
Enable Stage 2 Synchronization Interrupt
Definition
Disable Interrupt for Stage 2 Loss of
Synchronization
Enable Interrupt for Stage 2 Loss of
Synchronization
Definition
Disable Stage 1 Loss of Synchronization
Interrupt
Enable Stage 1 Loss of Synchronization
Interrupt
Definition
Disable Stage 1 Synchronization Interrupt
Enable Stage 1 Synchronization Interrupt
4
3
2
1
0