L64724 LSI Logic Corporation, L64724 Datasheet - Page 67

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table 3.5
3.6.1 PLL Parameter N (Group 4: APR 0)
(Sheet 4 of 4)
APR
[5:0]
58
59
60
61
62
63
64
65
66
67
68
69
Reserved
Serial_B
FMODE
D7
Group 4 Register Map (Cont.)
The PLL Configuration Parameter N (PLL_N[5:0]) configures the PLL
module for clock synthesis.
Read/Write: R/W
Set to 1
Reserved
Group 4: Configuration Registers
SPI_CLK_
APR
0
AND
D6
Serial_C[1:0]
Serial Transmission Start Data, TXSD[6:0]
Timing Lock Detector Threshold, CLK_LC_THSL[7:0]
Set to 1 Reserved
D7
SPI_MOD
Serial Transmission End Data, TXED[7:0]
E_A_B
Serial Transmission Data, STXD[7:0]
D5
Set to 1
This is an internal test bit that must be set to 1.
Reserved
This is an internal test bit that must be cleared to 0.
Reserved
D6
SPI_Bias[15:8] (MSB)
SPI_Bias[7:0] (LSB)
SPI_Gain[7:0](LSB)
served
Re-
D4
D5
Reserved
SPI_Bias[22:16]
D3
SPI_M[3:0]
PLL_N[5:0]
D2
SPI_N[3:0]
D1
SPI_Gain[9:8]
Reserved
Serial_A
DO
D0
3-37
7
6