L64724 LSI Logic Corporation, L64724 Datasheet - Page 85

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.20 Clock Divider (Group 4: APR 21)
This register is used to set the division ratio for the sampling clock.
Read/Write: R/W
PCLK_INV
PLL_BP
LCLK_OFF
CLK_DIV1
Group 4: Configuration Registers
APR
21
PCLK_INV PLL_BP LCLK_OFF
D7
PCLK Inversion
When the PCLK_INV bit is 0, the clock signal generated
internally is available on the PCLK pin. When the
PCLK_INV bit is 1, the polarity of the PCLK output
waveform is inverted.
PLL Bypass
When the PLL_BP bit is 0, the internal PLL module is
used to generate the clock for the ADC, Demodulator,
and FEC modules. When the bit is a 1, the PLL module
is bypassed and the PCLK signal is generated by dividing
the frequency of CLK by the value of CLK_DIV1. For
details, see Chapter 4.
LCLK OFF
The LCLK_OFF bit, when 0, turns off the LCLK signal.
When the LCLK_OFF bit is a 1, the LCLK signal is
turned on.
Input Division Factor for CLK
When the PLL module is bypassed (PLL_BP = 1), the
CLK_DIV1[4:0] field sets the input division factor for the
clock signal supplied to the L64724 on the CLK pin. The
CLK_DIV1[4:0] bits are not used when the PLL_BP bit is 0.
D6
D5
D4
CLK_DIV1[4:0]
D0
[4:0]
3-55
7
6
5