L64724 LSI Logic Corporation, L64724 Datasheet - Page 19
L64724
Manufacturer Part Number
L64724
Description
Satellite Receiver
Manufacturer
LSI Logic Corporation
Datasheet
1.L64724.pdf
(294 pages)
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1.3 Features Summary
This section summarizes the main features of the L64724. Subsequent
chapters describe these features in more detail.
Features Summary
On-chip self-tuning microcontroller acquisition and tracking,
eliminating microprocessor interaction, and simplifying software
development.
Supports DVB and DSS system specifications.
BPSK/QPSK demodulation rates from 1 to 45 Mbaud.
Matched filter (square root raised cosine filter with roll-off factor of
20% or 35%).
Antialiasing filters for operation from 1 to 45 MBaud without
switching external SAW filters or the need for low-pass filters.
On-chip digital clock synchronization.
On-chip digital carrier synchronization, featuring a frequency sweep
capability for signal acquisition.
Auto-acquisition demodulator mode and tuner control through an
on-chip microcontroller.
Integrated phase-locked loop (PLL) for clock synthesis, allowing the
use of a fundamental mode crystal.
Dual ADC.
Fast channel switching mode.
Power estimation for AGC control.
Programmable Viterbi decoder module for the following rates:
1/2, 2/3, 3/4, 5/6, 6/7, and 7/8.
(204/188), (146/130) Reed-Solomon decoder.
Auto-synchronization for the Viterbi decoder.
Programmable synchronization for the deinterleaver, Reed-Solomon
decoder, and descrambler.
Bit error monitoring for channel performance measurements.
Deinterleaver (DVB and DSS).
1-5
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