L64724 LSI Logic Corporation, L64724 Datasheet - Page 69

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

DVB_DSS
QB
PLL_T
Group 4: Configuration Registers
to 0 for IMQ to take effect. When IMQ_EN is set to a 1,
IMQ will be disregarded.
DVB/DSS Mode Select
The DVB_DSS bit indicates the format of the incoming
symbol stream. The L64724 supports data stream for-
mats that conform to either the Digital Video Broadcast
Standard (DVB) or the specifications for the Digital
Satellite System (DSS). Note that when DSS mode is
selected (DVB_DSS set to 1), the TEI indicator bit
(APR 3, D4) must be cleared to 0.
QPSK/BPSK Format Select
Set the QB bit to 1 to specify the format of the incoming
symbol stream. The QB bit should be cleared to 0 for
systems that input a QPSK symbol pair (I, Q) once per
CLK cycle. The QB bit should be set to 1 for BPSK input
(I stream only).
PLL Configuration Parameter T
PLL_T[4:0] is one of four parameters (PLL_S, PLL_N,
PLL_T, and PLL_M) that you must set to configure the
PLL module for clock synthesis. For more information,
see
Allowed values are 1 and all even numbers.
DVB_DSS
Section 4.2, “PLL Clock Generation,” page 4-3.
IMQ
QB
0
1
0
1
0
1
Symbol Format
I, Q
I,-Q
Symbol Format
DVB Format Selected
DSS Format Selected
Symbol Stream Format
QPSK
BPSK
[4:0]
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