L64724 LSI Logic Corporation, L64724 Datasheet - Page 7

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

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Contents
Synchronization, Tracking, and Loss of Sync for Three
Missed Sync Words
Minimum and Maximum Number of States in the
Acquisition Phase
Minimum and Maximum Number of States in the
Tracking Phase
DSS Packet
MPEG-2 Transport Packet
L64724 Transport Packet
Descrambler Synchronization
Viterbi Decoder Block Diagram
Puncturing and Depuncturing Block Diagram
Puncture Pattern for Different Code Rates
Block Diagram of Viterbi Bit Error Detection Circuit
Interleaving/Deinterleaving Operation for DVB
Interleaving/Deinterleaving Operation for DSS
Code Word Structure
FEC Data Path
122-Bit Burst Example
Descrambler Block Diagram
15-Bit Shift Register Initialization
Inverted Sync Words in Descrambler
AC Test Load and Waveform for Standard Outputs
AC Test Load and Waveforms for 3-State Outputs
L64724 Synchronous AC Timing
L64724 RESET Timing Diagram
L64724 Bus 3-State Delay Timing
L64724 Decoder Read Cycle
L64724 Decoder Write Cycle
100-Pin PQFP/MQFP Pinout
100-Pin PQFP/MQFP Mechanical Drawing
100-Pin PQFP/MQFP Mechanical Drawing (Cont.)
Serial Bus Architecture
7-Bit Slave Address for the L64724 Serial Bus
Serial Bus Write/Read Cycle Overview
General Call Structure
Burst Write or Single Write to Slave
(Master-Transmitter, Slave-Receiver)
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