L64724 LSI Logic Corporation, L64724 Datasheet - Page 171

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L64724

Manufacturer Part Number
L64724
Description
Satellite Receiver
Manufacturer
LSI Logic Corporation
Datasheet

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7.1 Viterbi Decoder Module
Chapter 7
The FEC Decoder
Pipeline
This chapter discusses the FEC Decoder Pipeline. The decoder pipeline
consists of four modules that are connected in a logical sequence. This
chapter discusses the four modules in the pipeline in the following sections:
The Viterbi Decoder contains the following major modules:
The block diagram in
L64724 Satellite Receiver
Section 7.1, “Viterbi Decoder Module”
Section 7.2, “Deinterleaver Module”
Section 7.3, “Reed-Solomon Decoder”
Section 7.4, “Descrambler Module Architecture and Operation”
Section 7.5, “FEC Module Software Reset”
A Depuncture Module for code rates other than 1/2
A 1/2 code rate Viterbi Decoder that computes the serial output data
stream given two sets of soft decision data input streams
A Synchronization Monitor to provide information on acquisition or
loss of synchronization
A Bit Error Rate (BER) Monitor
Figure 7.1
shows the Viterbi Decoder.
7-1

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