L64724 LSI Logic Corporation, L64724 Datasheet - Page 55

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.5.2 Reed-Solomon Uncorrected Error Count (Group 3: APR 2 and 3)
3.5.3 Viterbi Bit Error Rate Count (Group 3: APR 4 and 5)
3.5.4 Control Input, SNR, and Chip_ID register (Group 3: APR 6)
When read, the Reed-Solomon Uncorrected Error Count (UEC) register
presents the uncorrected blocks count since it was last reset. When
written, the register is cleared to 0. The UEC field is 16 bits long. The
LSB is located at APR 2, bit 0, and the MSB at APR 3, bit 7. The UEC
count saturates (stops) when it reaches its maximum count (65,535), and
the counter is not reset after it is read. When the register is written, the
UEC bits are cleared.
Read/Write: R/W
When read, the Viterbi Bit Error Rate Count register presents the Viterbi
decoder bit error count during the time period specified by VMDC2
(Group 4, APR 5,6,7). The Viterbi Bit Error rate Count (VBERC) field is
16 bits long. The LSB is located at APR 4, bit 0, and the MSB at APR
5, bit 7. The actual number of errors is equal to four times VBERC.
VBERC is updated each time a Viterbi error is encountered, and is reset
at the beginning of each VMDC2 period.
Read/Write: R
The Control Input, SNR, and Chip_ID register contains the Demodulator
Signal-to-Noise Ratio (Demod_SNR) bit, the Control Input bit (XCTR_IN),
and the Chip_ID bit.
Group 3: Status Registers
APR
APR
APR
APR
2
3
4
5
D15
D15
D7
D7
Reed-Solomon Uncorrected Error Count high byte, UEC[15:8]
Reed-Solomon Uncorrected Error Count low byte, UEC[7:0]
Viterbi Bit Error Rate Count high byte, VBERC[15:8]
Viterbi Bit Error Rate Count low byte, VBERC[7:0]
Reset Value: 0x0000
Reset Value: 0x0000
D0
D8
D0
D8
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