L64724 LSI Logic Corporation, L64724 Datasheet - Page 80

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3-50
Read/Write: R/W
Reserved
SSS[1:0]
SSA[1:0]
L64724 Registers
APR
16
D7
Reserved
Reserved
The Reserved bits must be cleared to 0 for proper
operation.
Synchronization Status/XCTR[3] Select
The SSS[1:0] bits allow you to observe the
synchronization status of one of the three
synchronization modules or the XCTR[3] output on the
XCTR[3] output pin. The synchronization modules that
may be observed are Viterbi Decoder synchronization,
Deinterleaver/Reed-Solomon Decoder synchronization,
and Descrambler synchronization. Program the SSS[1:0]
field to determine which one of these status bits will be
propagated to the XCTR[3] pin. Note that OS[4:0]
(Group 4, APR 17) should be set to 0b00000.
Synchronization States, Acquisition Mode
The second synchronization module (after the Viterbi
Decoder and before the Deinterleaver module) allows
three different state diagrams to be used in the
acquisition phase. The number of properly identified
synchronization words that will cause “in-synchronization”
to be declared can be configured from 3 to 6. For more
D6
0
0
1
1
SSS[1:0]
D5
SSS [1:0]
0
1
0
1
XCTR[3] Pin Connection
Viterbi decoder sync
DI/RS decoder sync
Descrambler sync
XCTR[3] (APR 55, D5)
D4
D3
SSA [1:0]
D2
D1
SST [1:0]
D0
[7:6]
[5:4]
[3:2]