L64724 LSI Logic Corporation, L64724 Datasheet - Page 118

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

4-4
Generated
Externally
The appropriate PCLK frequency is derived from CLK based on the
symbol rate of the underlying data stream and the Viterbi decoder rate
chosen. Due to the presence of an interpolator within the demodulator
module, PCLK will be slightly higher in frequency than the average
sampling rate for the demodulated symbol stream.
Based on the assumption that a 15 MHz external clock is available and
that the system data rate is chosen at 26 Mbaud, a sample calculation
for the L64724 clocking scheme is given in the following steps:
1. Determine the minimum PCLK required. Based on the data rate of
2. Determine PLL_T, PLL_S, PLL_M and PLL_N from
Figure 4.2
Note:
Channel Interfaces and Data Control
R = 200
C1 = 10 nF
C2 = 20 pF
CLK
26 MBaud, a PCLK frequency of at least 52 MHz must be generated.
CLK rate of 15 MHz. One acceptable set of values, for example, is
PLL_S = 14, PLL_N = 1, PLL_T = 4, and PLL_M = 1.
PLL Clock Synthesis
1/(PLL_T)
1/(PLL_S)
PLL Module
C1
LP2
R
PLL_M
Loop Filter
External
C2
PLLAGND
1/(PLL_N)
Table 4.1
for the
PCLK
Internal
Signal