L64724 LSI Logic Corporation, L64724 Datasheet - Page 117

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

4.2 PLL Clock Generation
The data control and clocking schemes presented in
Control and Clocking Schemes,” page
the generation of the external CLK signal required by the L64724. The
internal PLL generates the appropriate internal clock signal (PCLK) to
operate the ADC, demodulator, and FEC modules. The following clock
naming conventions are used in this section:
The L64724 contains a clock synthesizer to derive PCLK from CLK.
PCLK operates in the range of up to 90 MHz (see
scenario calls for the connection of a 15 or 60 MHz external signal to the
CLK pin as the basis for the internal PLL clock generation. It is also
possible to reuse the 4 MHz tuner crystal for L64724 clock generation
purposes.
The PLL can be configured to handle clock ratios for all data rates up to
45 Mbaud. The following registers must be set to derive the appropriate
clock frequencies:
LCLK is derived from CLK as shown in
Equation 4.1
PLL Clock Generation
LCLK
CLK–Input Clock supplied to L64724
PCLK–Sampling clock used to operate the ADC, demodulator, and
FEC modules. The on-chip PLL derives the PCLK signal from the
CLK signal.
LCLK–Clock generated by dividing the CLK input signal by the
CLK_DIV2 value.
PLL_T[4:0] (Group 4, APR 2)
PLL_N[5:0] (Group 4, APR 0)
PLL_S[5:0] (Group 4, APR 1)
PLL_M[1:0] (Group 4, APR 3)
=
---------------------------
CLKDIV 2
CLK
4-2, outline the requirements for
Equation
Figure
4.1.
Section 4.1, “Data
4.2). A common
4-3