LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 113

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks or primitives
and cascades them to create the memory sizes specified by the user in the Module Manager GUI. For memory
sizes smaller than an EBR block, the module will be created in one EBR block. In cases where the specified mem-
ory is larger than one EBR block, multiple EBR block can be cascaded, in depth or width (as required to create
these sizes).
The memory primitive for RAM_DQ for LatticeECP/EC devices is shown in Figure 8-6.
Figure 8-6. Single Port RAM Primitive or RAM_DQ for LatticeECP/EC Devices
In Single Port RAM mode the input data and address for the ports are registered at the input of the memory array.
The output data of the memory is optionally registered.
The various ports and their definitions for the Single Port Memory are included in Table 8-1. The table lists the cor-
responding ports for the module generated by Module Manager and for the EBR RAM_DQ primitive.
Table 8-1. EBR-based Single Port Memory Port Definitions
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can easily cascade eight memories. If the memory size specified by the user requires more than eight
EBR blocks, the software automatically generates the additional address decoding logic which is implemented in
the PFU (external to the EBR blocks).
Clock
ClockEn
Address
Data
Q
WE
Reset
—
Generated Module
Port Name in
AD[x:0]
CS[2:0]
DI[y:0]
CLK
CE
AD[x:0]
DI[y:0]
DO[y:0]
WE
RST
CS[2:0]
RST
CLK
WE
CE
EBR Block Primitive
Port Name in the
EBR
8-6
Clock
Clock Enable
Address Bus
Data In
Data Out
Write Enable
Reset
Chip Select
Description
DO[y:0]
for LatticeECP/EC Devices
Memory Usage Guide for
Rising Clock Edge
Active High
—
—
—
Active High
Active High
—
Active State