LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 227

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
time during transfer of the data, the INITN pin will be driven low by the LatticeECP/EC device. For handshaking
configurations, the CSN and CS1N pins can be driven low to pause configuration and stop the Master clock. The
BUSY pin can be used by the LatticeECP/EC device to pause the configuration host EC/ECP. Once the full data
stream has been shifted in, a CRC calculation done during configuration will be compared to the bit stream CRC. If
they match, then the device will either proceed to the Wake-up sequence or overflow the next data to the next
device. If the CRC does not match, then the INITN pin will be driven low and the device will remain in configuration
mode.
Wake Up the Device
When configuration is complete, the device should wake up in a predictable fashion. The following selections deter-
mine how the device will wake up. Two synchronous wake-up processes are available. One automatically wakes
the device up when the internal Done Bit is set even if the DONE pin is held low externally. The other waits for the
DONE pin to be driven high externally before starting the wake-up process. The DONE_EX preference determines
if the synchronous wake up will be controlled by the external driving of the DONE pin or ignores the external driving
of the DONE pin. Table 13-3 provides a list of the wake-up sequences supported by the devices.
Table 13-3. Wake-up Sequences supported by LatticeEC
Synchronous to Internal Done Bit
If the LatticeECP/EC device is the only device in the chain or the last device in a chain, the wake-up process should
be initiated by the completion of the configuration. Once the configuration is complete, the internal Done Bit will be
set and then the wake-up process will begin.
21 (Default)
Sequence
Default
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
1
2
3
4
5
6
7
8
9
DONE
DONE
DONE
DONE
DONE
DONE
DONE
Phase T0
GOE
GOE, GWDIS, GSR
GOE
GOE
GOE
GOE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
GOE
GOE, GWDIS
GWDIS
GWDIS, GSR
GOE, GSR
GOE, GWDIS, GSR
GOE
GOE, GWDIS
GWDIS
GWDIS, GSR
GOE, GSR
Phase T1
13-13
GSR, GWDIS
GOE, GWDIS, GSR
GWDIS, GSR
GWDIS
GSR
GOE, GWDIS, GSR
GWDIS, GSR
GOE
DONE
DONE
DONE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GOE, GSR
GOE
GWDIS
Lattice ECP/EC sysCONFIG Usage Guide
Phase T2
DONE
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GWDIS
GOE, GWDIS, GSR
GOE
GWDIS, GSR
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GOE, GSR
GOE
GWDIS
DONE
DONE
DONE
DONE
DONE
DONE
DONE
Phase T3