LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 2

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

www.latticesemi.com
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
June 2004
Section I. LatticeECP/EC Family Data Sheet
Introduction
Architecture
Features ............................................................................................................................................................. 1-1
Introduction ........................................................................................................................................................ 1-2
Architecture Overview ........................................................................................................................................ 2-1
PFU and PFF Blocks.......................................................................................................................................... 2-3
Routing............................................................................................................................................................... 2-6
Clock Distribution Network ................................................................................................................................. 2-7
sysMEM Memory ............................................................................................................................................. 2-10
sysDSP Block................................................................................................................................................... 2-12
Programmable I/O Cells (PIC) ......................................................................................................................... 2-19
DDR Memory Support...................................................................................................................................... 2-24
sysIO Buffer ..................................................................................................................................................... 2-26
Configuration and Testing ................................................................................................................................ 2-31
Slice .......................................................................................................................................................... 2-3
Primary Clock Sources.............................................................................................................................. 2-7
Clock Routing............................................................................................................................................ 2-7
sysCLOCK Phase Locked Loops (PLLs) .................................................................................................. 2-8
sysMEM Memory Block........................................................................................................................... 2-10
Bus Size Matching .................................................................................................................................. 2-10
RAM Initialization and ROM Operation ................................................................................................... 2-10
Memory Cascading ................................................................................................................................. 2-10
Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-10
Memory Core Reset ................................................................................................................................ 2-11
sysDSP Block Approach Compare to General DSP ............................................................................... 2-12
sysDSP Block Capabilities ...................................................................................................................... 2-13
MULT sysDSP Element .......................................................................................................................... 2-14
MAC sysDSP Element ............................................................................................................................ 2-14
MULTADD sysDSP Element................................................................................................................... 2-15
MULTADDSUM sysDSP Element........................................................................................................... 2-16
Clock, Clock Enable and Reset Resources ............................................................................................ 2-16
Signed and Unsigned with Different Widths............................................................................................ 2-17
OVERFLOW Flag from MAC .................................................................................................................. 2-17
ispLEVER Module Manager.................................................................................................................... 2-18
Optimized DSP Functions ....................................................................................................................... 2-18
Resources Available in the LatticeECP Family ....................................................................................... 2-18
DSP Performance of the LatticeECP Family........................................................................................... 2-18
PIO .......................................................................................................................................................... 2-20
DLL Calibrated DQS Delay Block ........................................................................................................... 2-24
Polarity Control Logic .............................................................................................................................. 2-26
sysIO Buffer Banks ................................................................................................................................. 2-26
Supported Standards .............................................................................................................................. 2-28
Hot Socketing.......................................................................................................................................... 2-30
IEEE 1149.1-Compliant Boundary Scan Testability................................................................................ 2-31
Device Configuration............................................................................................................................... 2-31
Internal Logic Analyzer Capability (ispTRACY)....................................................................................... 2-31
External Resistor..................................................................................................................................... 2-31
LatticeECP/EC Family Handbook
1
Table of Contents
TOC_01