LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 135

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 9-3. DQSBUFB Ports
Notes:
VHDL Usage:
--Component declaration
component DQSBUFB
end component;
--Module instantiation
U8 : DQSBUFB PORT MAP( DQSI => DQS,
Verilog Usage:
//Module instantiation
DQSBUFB U8 (.DQSI(DQS), .CLK(CLK), .READ(READ), .DQSDEL(dqsdel),
port(
1. The DDR Clock Polarity output from this block should be connected to the DDCLKPOL inputs of the input
2. If the delay in the DQSDLL is manually assigned then in order to see this dynamic delay in the DQSBUFB
DQSI
CLK
READ
DQSDEL
DDRCLKPOL: in STD_LOGIC;
DQSC
PRMBDET
DQSO
register blocks (IDDRXB).
block, software requires that you to also assign the attributes DEL_VAL and DEL_ADJ with the DQSBUF
primitive.
DQSI
CLK
READ
DQSDEL
DQSO
DQSC
DDRCLKPOL
PRMBDET
Port Name
.DDRCLKPOL (ddrclkpol_sig),.DQSC(DQSCIB), .PRMBDET(PRMBDET),
.DQSO(dqsbuf));
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
:
: out STD_LOGIC;
: out STD_LOGIC);
CLK
READ
DQSDEL => dqsdel,
DDRCLKPOL =>ddrclkpol_sig,
DQSC => DQSCIB,
PRMBDET =>PRMBDET,
DQSO =>dqsbuf);
out STD_LOGIC;
=> CLK,
=> READIN,
I/O
O
O
O
O
I
I
I
I
DQS strobe signal from memory
System CLK
Read generated from the FPGA core
DQS delay from the DQSDLL primitive
Delayed DQS Strobe signal, to the input capture register block
DQS Strobe signal before delay, going to the FPGA core logic
DDR Clock Polarity signal
Preamble detect signal, going to the FPGA core logic
9-6
Definition
Lattice ECP/EC DDR Usage Guide