LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 98

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Assigning V
Each bank has two dedicated V
V
PGROUP preference.
Preference Syntax
PGROUP <pgrp_name> [(VREF <vref_name>)+] (COMP <comp_name>)+;
LOCATE PGROUP <pgrp_name> BANK <bank_num>;
LOCATE VREF <vref_name> SITE <site_name>;
Example of VREF Groups
PGROUP “vref_pg1” VREF “ref1” COMP “ah(0)” COMP “ah(1)” COMP “ah(2)” COMP “ah(3)”
COMP “ah(4)” COMP “ah(5)” COMP “ah(6)” COMP “ah(7)”;
PGROUP “vref_pg2” VREF “ref2” COMP “al(0)” COMP “al(1)” COMP “al(2)” COMP “al(3)”
COMP “al(4)” COMP “al(5)” COMP “al(6)” COMP “al(7)”;
LOCATE VREF “ref1” SITE PR29C;
LOCATE VREF “ref2” SITE PR48B;
or
LOCATE PGROUP “ vref_pg1” BANK 2;
LOCATE PGROUP “ vref_pg2” BANK 2;
The second example show V
must then be locked to either V
which bank V
If the PGROUP VREF is not used, the software will automatically group all pins that need the same V
voltage. This preference is most useful when there is more than one bus using the same reference voltage and the
user wants to associate each of these buses to different V
Differential I/O Implementation
The LatticeECP/EC devices support a variety of differential standards as detailed in the following section.
LVDS
True LVDS (LVDS25) drivers are available on the left and right side of the devices. LVDS input support is provided
on all sides of the device. All four sides support LVDS using complementary LVCMOS drivers with external resis-
tors (LVDS25E).
Please refer to the LatticeECP/EC Family Data Sheet for a more detailed explanation of these LVDS implementa-
tions.
LVPECL
All the sysIO Buffers will support LVPECL inputs. LVPECL outputs are supported using a complementary LVCMOS
driver with external resistors.
Please refer to the LatticeECP/EC Family Data Sheet for further information on LVPECL implementation.
BLVDS
All single-ended sysIO buffer pairs in the LatticeECP family support the Bus-LVDS standard using complementary
LVCMOS drivers with external resistors.
REF1
or V
REF2.
REF
REF
group should be located. The software will then assign these to either V
This grouping is done by assigning a PGROUP VREF preference along with the LOCATE
/ V
REF
Groups for Referenced Inputs
REF
REF
REF1
groups, “vref_pg1” assigned to V
input pins, V
or V
REF2
using LOCATE preference. Or, the user can simply designate to
REF1
and V
7-10
REF
REF2.
resources.
REF
Buffers can be grouped to a particular V
“ref1” and “vref_pg2” assigned to “ref2”. V
LatticeECP/EC sysIO Usage Guide
REF1
or V
REF2
REF
of the bank.
reference
REF
rail,
REF