LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 22
LFEC10E-3F256C
Manufacturer Part Number
LFEC10E-3F256C
Description
Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.LFEC10E-3F256C.pdf
(231 pages)
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Figure 2-12. Memory Core Reset
For further information on sysMEM EBR block, please see the details of additional technical documentation at the
end of this data sheet.
sysDSP Block
The LatticeECP-DSP family provides a sysDSP block making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
(FIR) filters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing appropriate level of parallelism. Figure 2-13 compares the serial and the
parallel implementations.
GSRN
RSTA
RSTB
Programmable Disable
Memory Core
2-12
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeECP/EC Family Data Sheet
Port A[17:0]
Port B[17:0]
Architecture
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