LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 35

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS rout-
ing resource. The DQS signal also feeds polarity control logic which controls the polarity of the clock to the sync
registers in the input register blocks. Figures 2-27 and 2-28 show how the DQS transition signals are routed to the
PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of
the device as shown in Figure 2-28. The DLL loop is compensated for temperature, voltage and process variations
by the system clock and feedback loop.
Figure 2-27. DQS Local Bus.
Control
Polarity
Control
Delay
DQS
Bus
Bus
Bus
DQS
DQS
CLKI
GSR
DQS
CEI
To DDR
Reg.
Polarity Control
Register Block
( 5 Flip Flops)
2-25
PIO
PIO
DQSDEL
Logic
Input
To Sync.
Calibration Bus
from DLL
Reg.
LatticeECP/EC Family Data Sheet
Buffer
Buffer
sysIO
sysIO
DI
DI
Datain
Strobe
DDR
DQS
PAD
PAD
Architecture