LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 94

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Actual options available vary by I/O voltage. The user must consider the maximum allowable current per bank and
the package thermal limit current when selecting the drive strength.
Programmable Slew Rate
Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows slew
rate control to be specified on pin-by-pin basis. This slew rate control affects both the rising edges and the falling
edges.
In addition to these configurations, each individual sysIO buffer also has a tristate control capability along with open
drain control.
Open Drain Control
When configured as LVCMOS or LVTTL, the drivers support open drain operation on each I/O independently.
When an I/O is configured as an open drain, the pull-up transistors on the pad are permanently disabled.
Differential SSTL and HSTL Support
The single-ended driver associated with the complementary ‘C’ pad can optionally be driven by the complement of
the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers
to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driv-
ing complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on syn-
chronous DRAM and synchronous SRAM devices respectively). This capability is also used in conjunction with off-
chip resistors to emulate LVPECL and BLVDS output drivers.
PCI Support
Each sysIO buffer can be configured to support PCI33. The buffers on the top and bottom of the device have an
optional PCI clamp diode that may optionally be specified in the ispLEVER
Programmable Input Delay
Each input can optionally be delayed before it is passed to the core logic or input registers. The primary use for the
input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. To arrive at
zero hold time, the input delay will delay the data by at least as much as the primary clock injection delay. This
option can be turned ON or OFF for each I/O independently in the software using the FIXEDDELAY attribute. This
attribute is described in more detail in the Software sysIO Attributes section. Appendix A shows how this feature
can be enabled in the software using HDL attributes.
5V Tolerant Input Buffers
All the I/Os have a clamp diode that is used to clamp the voltage at the input to V
PCI I/O standards. This clamp diode can be used along with an external resistor to make an input 5V tolerant.
Figure 7-2. 5V Tolerant Input Buffer
5V Signals from
Legacy Systems
External
Resistor
7-6
LatticeECP/EC sysIO Usage Guide
®
design tool.
3.3V
CCIO.
This is especially useful for