LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 118
LFEC10E-3F256C
Manufacturer Part Number
LFEC10E-3F256C
Description
Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.LFEC10E-3F256C.pdf
(231 pages)
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Table 8-7. EBR based Pseudo-Dual Port Memory Port Definitions
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can cascade eight memories easily. However, if the memory size specified by the user requires more than
eight EBR blocks, the software automatically generates the additional address decoding logic, which is imple-
mented in the PFU (external to the EBR blocks).
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 8-8.
Table 8-8. Pseudo-Dual Port Memory Sizes for 9K Memory for LatticeECP/EC Devices
Table 8-9 shows the various attributes available for the Pseudo Dual Port Memory (RAM_DP). Some of these
attributes are user selectable through the Module Manager GUI. For detailed attribute definitions, refer to Appendix
A.
Pseudo-Dual
Port Memory
512 x 18
8K x 1
4K x 2
2K x 4
1K x 9
Size
RdAddress
WrAddress
RdClock
WrClock
RdClockEn
WrClockEn
Q
Data
WE
Reset
—
Generated Module
Port Name in
Input Data
DIA[17:0]
DIA[1:0]
DIA[3:0]
DIA[8:0]
Port A
DIA
ADR[x:0]
ADW[x:0]
CLKR
CLKW
CER
CEW
DO[y:0]
DI[y:0]
WE
RST
CS[2:0]
Port Name in the EBR
Input Data
DIB[17:0]
DIB[1:0]
DIB[3:0]
DIB[8:0]
Block Primitive
Port B
DIB
Output Data
DOA[17:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
Port A
8-11
DOA
Read Address
Write Address
Read Clock
Write Clock
Read Clock Enable
Write Clock Enable
Read Data
Write Data
Write Enable
Reset
Chip Select
Description
Output Data
DOB[17:0]
DOB[1:0]
DOB[3:0]
DOB[8:0]
Port B
DOB
for LatticeECP/EC Devices
Memory Usage Guide for
—
—
Rising Clock Edge
Rising Clock Edge
Active High
Active High
—
—
Active High
Active High
—
Read Address
[MSB:LSB]
RAD[12:0]
RAD[11:0]
RAD[10:0]
RAD[9:0]
RAD[9:0]
Port A
Active State
Write Address
[MSB:LSB]
WAD[12:0]
WAD[11:0]
WAD[10:0]
WAD[9:0]
WAD[9:0]
Port B
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