LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 29

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-19. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
Figure 2-19. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-20.
The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device
can be configured as LVDS transmit/receive pairs.
One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds
the DQS bus which spans the set of 16 PIOs. The DQS signal from the bus is used to strobe the DDR data from the
memory into input register blocks. This interface is designed for memories that support one DQS strobe per eight
bits of data.
DDRCLKPOL
ONEG1
ONEG0
OPOS1
OPOS0
IPOS0
IPOS1
GSRN
INCK
INDD
INFF
DQS
CLK
LSR
CE
TD
Control
Muxes
CLKO
CEO
GSR
CLKI
LSR
CEI
PIO B
PIO A
TD
D0
D1
DDRCLK
D0
D1
DDRCLK
INCK
INDD
INFF
IPOS0
IPOS1
Register Block
Register Block
Register Block
(2 Flip Flops)
(2 Flip Flops)
(5 Flip Flops)
2-19
Tristate
Output
Input
IOLD0
IOLT0
DI
LatticeECP/EC Family Data Sheet
Buffer
sysIO
PADB
PADA
"C"
"T"
Architecture