LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 114

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 8-2.
Table 8-2. Single Port Memory Sizes for 9K Memories for LatticeECP/ EC Devices
Table 8-3 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes
are user selectable through the Module Manager GUI. For detailed attribute definitions, refer to Appendix A.
Table 8-3. Single Port RAM Attributes for LatticeECP/ EC Devices
True Dual Port RAM (RAM_DP_TRUE) – EBR Based
The EBR blocks in the LatticeECP/EC devices can be configured as True-Dual Port RAM or RAM_DP_TRUE. Mod-
ule Manager allows users to generate the Verilog-HDL, VHDL or EDIF netlists for the memory size as per design
requirements.
The Module Manager generates the memory module as shown in Figure 8-7.
Figure 8-7. True Dual Port Memory Module Generated by Module Manager
DATA_WIDTH
REGMODE
RESETMODE
CSDECODE
WRITEMODE
GSR
Attribute
Memory Size
Single Port
Data Word Width
Register Mode (Pipelining) NOREG, OUTREG
Selects the Reset type
Chip Select Decode
Read / Write Mode
Global Set Reset
512 x 18
256 x 36
8K x 1
4K x 2
2K x 4
1K x 9
Description
WrAddressA
ClockEnA
ResetA
ClockA
DataA
WEA
QA
Input Data
DI[17:0]
DI[35:0]
1, 2, 4, 9, 18, 36
ASYNC, SYNC
000, 001, 010, 011, 100, 101, 110,
111
NORMAL, WRITETHROUGH,
READBEFOREWRITE
ENABLE, DISABLE
DI[1:0]
DI[3:0]
DI[8:0]
DI
Dual Port Memory
EBR-based True
RAM_DP_TRUE
Values
8-7
Output Data
DO[17:0]
DO[35:0]
DO[1:0]
DO[3:0]
DO[8:0]
DO
ClockB
ClockEnB
ResetB
WEB
WrAddressB
DataB
QB
NORMAL
1
NOREG
ASYNC
000
ENABLED
Default Value
for LatticeECP/EC Devices
Memory Usage Guide for
Address [MSB:LSB]
AD[12:0]
AD[11:0]
AD[10:0]
AD[9:0]
AD[8:0]
AD[7:0]
Through Module
User Selectable
Manager
YES
YES
YES
YES
YES
NO