LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 224

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
If either overflow option is selected, the CSN or CS1N pins can be toggled to reset the Master Parallel device out of
the Overflow option, otherwise both chip select pins should be held low to keep the device active for configuration.
Figure 13-6. Master and Slave Parallel Daisy Chain
Slave Parallel Mode
In Slave Parallel Mode, a host system sends the configuration data in a byte wide stream to the device. The CCLK,
CSN, CS1N and the WRITEN signal are provided by the host system such as a Master Parallel mode device as
shown in Figure 13-6.
The Slave Parallel configuration mode allows multiple devices to be chained in parallel.
To support asynchronous configuration, where the host may provide data faster than the FPGA can handle it, the
Slave Parallel mode can use the BUSY signal. By driving the BUSY signal high, the Slave Parallel device tells the
host to pause sending data.
Slave Parallel (no overflow option)
Slave Parallel (Bypass ON)
Slave Parallel (Flow Through ON)
RESET/OE
PROM
Mode
D[0:7]
CLK
CS
WRITEN
CCLK
D[0:7]
DONE
INITN
CSN
CS1N
PROGRAMN
CFG[2]
Master Parallel
Lattice FPGA
1
1
1
DOUT/CSON
13-10
CFG[1]
CFG2
CFG1
CFG0
1
1
1
Lattice ECP/EC sysCONFIG Usage Guide
CFG[0]
1
1
1
CCLK
D[0:7]
DONE
INITN
WRITEN
CSN
CS1N
PROGRAMN
SLAVE_PARALLEL
SLAVE_PARALLEL_BYPASS
SLAVE_PARALLEL_FLOWTHR
Lattice FPGA
Slave Parallel
CONFIG_MODE Parameter
CFG2
CFG1
CFG0