LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 123

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Memory Usage Guide for
Lattice Semiconductor
for LatticeECP/EC Devices
FIFO Reset
A FIFO reset will clear the contents of the FIFO by resetting the read and write pointers as well as put the FIFO
flags in the initial reset state.
Read Pointer Reset
The purpose of the read pointer reset is to indicate retransmit, and is most commonly used in “packetized” commu-
nications. In this application, the user must keep careful track of when a packet is written into or read from the
FIFO.
Register Mode
There are two modes for registering and pipelining the read and write cycles of the memory. In the minimum mode,
a single set of input registers allows synchronous write cycles into the memory array with the other register banks
bypassed. The additional mode includes using the output registers.
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based
PFU-based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create larger distributed memory sizes.
Figure 8-15 shows the Distributed Single Port RAM module as generated by the Module Manager.
Figure 8-15. Distributed Single Port RAM Module Generated by Module Manager
Clock
ClockEn
Reset
PFU based
Distributed Single Port
Q
Memory
WE
Address
Data
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is
generated by utilizing the resources available in the PFU. The basic Distributed Single Port RAM primitive for the
LatticeECP/EC devices is shown in Figure 8-16.
8-16