LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 28

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispLEVER Module Manager
The user can access the sysDSP block via the ispLEVER Module Manager, which has options to configure each
DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Math-
works to support instantiation in the Simulink tool, which is a Graphical Simulation Environment. Simulink works
with ispLEVER and dramatically shortens the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor-
relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo
Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available
DSP IPs.
Resources Available in the LatticeECP Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows
the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed
RAM can be used to store variables locally for the fast DSP operations.
Table 2-9. Number of DSP Blocks in LatticeECP Family
Table 2-10. Embedded SRAM in LatticeECP family
DSP Performance of the LatticeECP Family
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP family.
Table 2-11. DSP Block performance of LatticeECP Family
For further information on the sysDSP block, please see details of additional technical information at the end of this
data sheet.
LFECP10
LFECP15
LFECP20
LFECP40
LFECP6
Device
DSP Block
LFECP10
LFECP15
LFECP20
LFECP40
LFECP10
LFECP15
LFECP20
LFECP40
LFECP6
LFECP6
Device
Device
10
4
5
6
7
EBR SRAM Block
9x9 Multiplier
DSP Block
2-18
32
40
48
56
80
10
30
38
46
70
10
4
5
6
7
DSP Performance
Total EBR SRAM
18x18 Multiplier
LatticeECP/EC Family Data Sheet
(Kbits)
MMAC
276
350
424
645
16
20
24
28
40
92
36x36 Multiplier
10
4
5
6
7
Architecture