sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 132

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Generator (S08ICGV4)
is very flexible, and in some configurations, it is possible to exceed certain clock specifications. When
using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value
to ensure proper MCU operation.
8.5.1
Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state.
However there are two cases to consider when clock activity continues while the CPU is in stop mode,
8.5.1.1
When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to
memory and control registers via the BDC controller.
8.5.1.2
When the oscillator is enabled in stop mode (OSCSTEN = 1), the individual clock generators are enabled
but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator
startup times if necessary, or to run the RTI from the oscillator during stop3.
8.5.1.3
Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system
clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock
is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT.
Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the
default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an
approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096
clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time.
8.5.2
Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following
conditions occur:
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by f
into the filter registers (ICGFLTH and ICGFLTL). This is the only mode in which the filter registers can
be written.
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ICGDCLK
After any reset.
Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state
temporarily until the DCO is stable (DCOS = 1).
CLKS bits are written from X1 to 00.
CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1).
Off Mode (Off)
Self-Clocked Mode (SCM)
/ R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
BDM Active
OSCSTEN Bit Set
Stop/Off Mode Recovery
SC9S08MZ16 MCU Data Sheet, Rev. 1
Freescale Semiconductor