sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 183

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

10.2.4
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) are used to clear these status flags.
Freescale Semiconductor
Reset
Field
RWU
SBK
RE
2
1
0
W
R
TDRE
SCI Status Register 1 (SCIxS1)
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If
LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.
0 Receiver off.
1 Receiver on.
Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a
second break character may be queued before software clears SBK. Refer to
Queued
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
1
7
Idle” for more details.
= Unimplemented or Reserved
TC
1
6
Table 10-4. SCIxC2 Field Descriptions (continued)
Figure 10-8. SCI Status Register 1 (SCIxS1)
RDRF
SC9S08MZ16 MCU Data Sheet, Rev. 1
0
5
IDLE
Section 10.3.3.2, “Receiver Wakeup
0
4
Description
OR
3
0
Serial Communications Interface (S08SCIV4)
NF
0
2
Section 10.3.2.1, “Send Break and
Operation” for more details.
FE
0
1
PF
0
0
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