sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 134

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Generator (S08ICGV4)
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
8.5.4
FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from
the subtractor is greater than the maximum n
lock detector to detect the unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n
the minimum n
In this state the output clock signal ICGOUT frequency is given by f
8.5.5
FLL engaged internal locked is entered from FEI unlocked when the count error (Δn), which comes from
the subtractor, is less than n
required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is
given by f
The update made is an average of the error measurements taken in the four previous comparisons.
8.5.6
FLL bypassed external (FBE) is entered when any of the following conditions occur:
In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,
ICGERCLK. The output clock signal ICGOUT frequency is given by f
source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range
0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for
RANGE = 0 or high for RANGE = 1.
8.5.7
The FLL engaged external (FEE) mode is entered when any of the following conditions occur:
In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The
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From SCM when CLKS = 10 and ERCS is high
When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited
From FLL engaged external mode if a loss of DCO clock occurs and the external reference remains
valid (both LOCS = 1 and ERCS = 1)
CLKS = 11 and ERCS and DCOS are both high.
The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
ICGDCLK
FLL Engaged Internal Unlocked
FLL Engaged Internal Locked
FLL Bypassed, External Clock (FBE) Mode
FLL Engaged, External Clock (FEE) Mode
lock
, as required by the lock detector to detect the lock condition.
/ R. In FEI locked, the filter value is updated only once every four comparison cycles.
lock
(max) and greater than n
SC9S08MZ16 MCU Data Sheet, Rev. 1
unlock
or less than the minimum n
lock
(min) for a given number of samples, as
ICGDCLK
ICGERCLK
unlock
/ R.
/ R. If an external clock
, as required by the
Freescale Semiconductor
lock
or less than