sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 197

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sc9s08mz16

Manufacturer Part Number
sc9s08mz16
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
11.2
The ADC channel assignments for the SC9S08MZ16 are shown in the table below. Channels that are
unimplemented are internally connected to V
Channels which are connected to an I/O pin have an associated pin control bit as shown.
11.2.1
The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided
by two, the local asynchronous clock (ADACK) within the module, or the alternate clock, ALTCLK. The
alternate clock for the SC9S08MZ16 MCU devices is the external reference clock (ICGERCLK) from the
internal clock generator (ICG) module.
Because ICGERCLK is active only while an external clock source is enabled, the ICG must be configured
for either FBE or FEE mode (CLKS1 = 1). ICGERCLK must run at a frequency such that the ADC
conversion clock (ADCK) runs at a frequency within its specified range (f
from the ALTCLK input as determined by the ADIV bits. For example, if the ADIV bits are set up to divide
by four, then the minimum frequency for ALTCLK (ICGERCLK) is four times the minimum value for
Freescale Semiconductor
ADCH
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Channel Assignments
Channel
Alternate Clock
AD10
AD11
AD12
AD13
AD14
AD15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
Selecting the internal bandgap channel requires BGBE =1 in SPMSC1 see
Section 5.9.8, “System Power Management Status and Control 1 Register
(SPMSC1).” For value of bandgap voltage reference see
Characteristics.”
PTB2/TPM3CH1
PTB3/TPM3CH0
PTD2/AD1P10
PTD3/AD1P11
PTB0/AD1P0
PTB1/AD1P1
PTD0/AD1P8
PTD1/AD1P9
/AD1P2
/AD1P3
V
V
V
V
V
V
V
V
Input
REFL
REFL
REFL
REFL
REFL
REFL
REFL
REFL
Table 11-1. ADC Channel Assignment
SC9S08MZ16 MCU Data Sheet, Rev. 1
Pin Control
ADPC10
ADPC11
ADPC0
ADPC1
ADPC2
ADPC3
ADPC8
ADPC9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REFL .
NOTE
Reserved channels convert to an unknown value.
ADCH
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Chapter 11 Analog-to-Digital Converter (S08ADC10V1)
Channel
disabled
module
V
V
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
REFH
REFL
Section A.5, “DC
ADCK
Internal Bandgap
Temp Sensor
Reserved
Reserved
Reserved
) after being divided down
Reserved
Reserved
V
V
V
V
V
V
V
V
Input
None
REFH
REFL
REFL
REFL
REFL
REFL
REFL
REFL
Pin Control
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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