sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 92

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sc9s08mz16

Manufacturer Part Number
sc9s08mz16
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Note: Bits 7 through 4 are reserved bits that must always be written to 0.
Note: Bits 7 through 4 are reserved bits that must always be written to 0.
Note: Bits 7 through 4 are reserved bits that must always be written to 0.
Chapter 6 Parallel Input/Output
6.7.8
In addition to the I/O control, port D pins are controlled by the registers listed below.
92
PTDDD[3:0]
PTDPE[3:0]
Reset
Reset
Reset
Field
Field
3:0
3:0
W
W
W
R
R
R
Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port D bit n.
1 Internal pullup device enabled for port D bit n.
R
R
R
0
0
0
7
7
7
Figure 6-28. Output Slew Rate Control Enable for Port D (PTDSE)
R
R
R
0
0
0
6
6
6
Figure 6-27. Internal Pullup Enable for Port D (PTDPE)
Table 6-18. PTDPE Register Field Descriptions
Table 6-17. PTDDD Register Field Descriptions
Figure 6-26. Data Direction for Port D (PTDDD)
SC9S08MZ16 MCU Data Sheet, Rev. 0 Draft C
R
R
R
0
0
0
5
5
5
R
R
R
0
0
0
4
4
4
Description
Description
PTDDD3
PTDPE3
PTDSE3
3
0
3
0
3
0
PTDDD2
PTDPE2
PTDSE2
0
0
0
2
2
2
PTDDD1
PTDPE1
PTDSE1
Freescale Semiconductor
0
0
0
1
1
1
PTDDD0
PTDPE0
PTDSE0
0
0
0
0
0
0

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