sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 93

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Note: Bits 7 through 4 are reserved bits that must always be written to 0.
6.7.9
Port E parallel I/O function is controlled by the registers listed below.
Freescale Semiconductor
PTDSE[3:0]
PTDDS[3:0]
PTED[7:0]
Reset
Reset
Field
Field
Field
3:0
3:0
7:0
W
W
R
R
PTED7
Port E I/O Registers (PTED and PTEDD)
Output Slew Rate Control Enable for Port D Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
output drive for the associated PTD pin.
0 Low output drive enabled for port D bit n.
1 High output drive enabled for port D bit n.
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
R
0
0
7
7
Figure 6-29. Output Drive Strength Selection for Port D (PTDDS)
PTED6
R
0
0
6
6
Table 6-20. PTDDS Register Field Descriptions
Table 6-19. PTDSE Register Field Descriptions
Table 6-21. PTED Register Field Descriptions
Figure 6-30. Port E Data Register (PTED)
SC9S08MZ16 MCU Data Sheet, Rev. 0 Draft C
PTED5
R
0
0
5
5
PTED4
R
0
0
4
4
Description
Description
Description
PTDDS3
PTED3
3
0
3
0
PTDDS2
PTED2
0
0
2
2
Chapter 6 Parallel Input/Output
PTDDS1
PTED1
0
0
1
1
PTDDS0
PTED0
0
0
0
0
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