sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 70

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Resets, Interrupts, and System Configuration
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
should be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
5.9.5
This register is used to control the MCLK clock output.
70
Reset
Reset
MCSEL
STOPE
COPE
COPT
Field
Field
MPE
2:0
7
6
5
4
W
W
R
R
COPE
System MCLK Control Register (SMCLK)
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.1Stop mode enabled.
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See
1
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
COPT
1
0
0
6
6
Figure 5-6. System MCLK Control Register (SMCLK)
Table 5-7. SMCLK Register Field Descriptions
Figure 5-5. System Options Register (SOPT)
Table 5-6. SOPT Register Field Descriptions
SC9S08MZ16 MCU Data Sheet, Rev. 0 Draft C
STOPE
0
0
0
5
5
Equation
MPE
1
0
4
4
5-1.
Description
Description
3
0
0
3
0
0
0
0
0
2
2
Freescale Semiconductor
MCSEL
1
0
1
1
1
0
0
0