sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 34

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 3 Modes of Operation
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.5.2
To enter stop3, the user must execute a STOP instruction with stop3 selected (PPDC = 0) and stop mode
enabled (STOPE = 1). Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator
itself, are halted. The ICG enters its standby state, as does the voltage regulator and the ADC. The states
of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are
not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic
driving the pins being maintained.
Exit from stop3 is done by asserting RESET or by an interrupt from one of the following sources: the
real-time interrupt (RTI), LVD system, ADC, IRQ, or SCI.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1 kHz source are disabled. Power consumption is lower when the 1 kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
3.5.3
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in
the CPU executes a STOP instruction, the system clocks to the background debug logic remain active
when the MCU enters stop mode so background debug communication is still possible. In addition, the
voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the
user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in stop mode. The
BACKGROUND command can be used to wake the MCU from stop and enter active background mode
if the ENBDM bit is set. After entering background debug mode, all background commands are available.
Table 3-2
enabled.
34
Mode
Stop3
summarizes the behavior of the MCU in stop when entry into the background debug mode is
Stop3 Mode
Active BDM Enabled in Stop Mode
PPDC
0
CPU, Digital
Peripherals,
Standby
Flash
Chapter 12, “Development
Table 3-2. BDM Enabled Stop Mode Behavior
SC9S08MZ16 MCU Data Sheet, Rev. 0 Draft C
Standby
RAM
Active
ICG
Optionally on
Support” of this data sheet. If ENBDM is set when
ADC
Regulator
Active
States held Optionally on
I/O Pins
Freescale Semiconductor
RTI