sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 135

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.
The minimum multiplier for the FLL, from
operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
8.5.7.1
FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater
than the maximum n
unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n
the minimum n
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by f
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. After the FLL has locked, if an unexpected loss of lock
causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal
ICGOUT frequency is given by f
8.5.7.2
FEE locked is entered from FEE unlocked when the count error (Δn) is less than n
than n
condition. The output clock signal ICGOUT frequency is given by f
locked, the filter value is updated only once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
8.5.8
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see
the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn. To
achieve locked status, Δn must be between n
stay between n
the LOLS status bit is set and remains set until cleared by software or until the MCU is reset. LOLS is
cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset
(LOLRE = 1), or by any MCU reset.
If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked
status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock
condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters
the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up
from stop.
Freescale Semiconductor
lock
(min) for a given number of samples, as required by the lock detector to detect the lock
FLL Lock and Loss-of-Lock Detection
FLL Engaged External Unlocked
FLL Engaged External Locked
unlock
lock
, as required by the lock detector to detect the lock condition.
unlock
(min) and n
or less than the minimum n
Table 8-9
unlock
ICGDCLK
SC9S08MZ16 MCU Data Sheet, Rev. 1
(max) to remain locked. If Δn goes outside this range unexpectedly,
for explanation of a comparison cycle) and passes this number to
/ R.
Table 8-12
lock
(min) and n
unlock
is 4. Because 4 X 10 MHz is 40MHz, which is the
, as required by the lock detector to detect the
lock
(max). After the FLL has locked, Δn must
ICGDCLK
Internal Clock Generator (S08ICGV4)
/R. In FLL engaged external
lock
ICGDCLK
(max) and greater
lock
/ (2×R) This
or less than
135