sc9s08mz16 Freescale Semiconductor, Inc, sc9s08mz16 Datasheet - Page 87

• Manufacturer Part Number: sc9s08mz16
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Note: Bits 7 through 2 are reserved bits that must always be written to 0.
Note: Bits 7 through 4 are reserved bits that must always be written to 0.
6.7.3
Port B parallel I/O function is controlled by the registers in this section.
1.
Freescale Semiconductor
PTBD[3:0]
1
PTASEn
PTADSn
Reset
Reset
Field
Field
Field
1:0
1:0
3:0
W
W
R
R
Port B I/O Registers (PTBD and PTBDD)
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
R
R
0
0
7
7
Figure 6-14. Output Drive Strength Selection for Port A (PTADS)
R
R
0
0
6
6
Table 6-4. PTASE Register Field Descriptions
Table 6-5. PTADS Register Field Descriptions
Table 6-6. PTBD Register Field Descriptions
Figure 6-15. Port B Data Register (PTBD)
SC9S08MZ16 MCU Data Sheet, Rev. 0 Draft C
R
R
0
0
5
5
R
R
0
0
4
4
Description
Description
Description
PTBD3
R
3
0
3
0
PTBD2
R
0
0
2
2
Chapter 6 Parallel Input/Output
PTADS1
PTBD1
0
0
1
1
PTADS0
PTBD0
0
0
0
0
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