mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 11

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 3:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
M8, M3, M7,
N2, N8, N3,
P8, P3, M2,
Number
x16 Ball
L2, L3, L1
N7, P2,
K7, L7,
P7, R2
J8, K8
F3, B3
K9
K2
K3
R8
L8
84-/60-Ball Descriptions
x4, x8 Ball
H8, H3, H7,
K8, K3, H2,
G2, G3, G1
J2, J8, J3,
Number
F7, G7,
J7, K2,
K7, L2
E8, F8
G8
B3
F9
F2
F3
L8
L3
RAS#, CAS#,
A14 (x4, x8)
LDM, UDM
BA0–BA2
A11–A12
Symbol
A8–A10,
CK, CK#
A0–A2,
A3–A5,
A6–A7,
(DM)
ODT
WE#
CKE
A13
CS#
Input
Input
Input
Input
Input
Input
Input
Input
Type
Description
On-die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ15, LDM, UDM,
LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7, DQS, DQS#,
RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#, and DM
for the x4. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS/
DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2
SDRAM configuration and operating mode. CKE LOW provides
precharge power-down mode and SELF REFRESH operation (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry, power-down exit, output
disable, and for self refresh entry. CKE is asynchronous for SELF
REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are
disabled during power-down. Input buffers (excluding CKE) are
disabled during self refresh. CKE is an SSTL_18 input but will detect
a LVCMOS LOW level once V
After V
sequence, it must be maintained for proper operation of the CKE
receiver. For proper SELF REFRESH operation, V
maintained.
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external bank selection on
systems with multiple ranks. CS# is considered part of the command
code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM
balls are input-only, the DM loading is designed to match that of DQ
and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM
for upper byte DQ8–DQ15.
Bank address inputs: BA0–BA2 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0–BA2
define which mode register, including MR, EMR, EMR(2), and
EMR(3), is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA2–BA0) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
11
REF
has become stable during the power on and initialization
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignment and Description
2Gb: x4, x8, x16 DDR2 SDRAM
DD
is applied during first power-up.
©2006 Micron Technology, Inc. All rights reserved.
REF
must be