mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 64

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Power-Down Mode
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
DDR2 SDRAMs support multiple power-down modes that allow significant power
savings over normal operating modes. CKE is used to enter and exit different power-
down modes. Power-down entry and exit timings are shown in Figure 47 on page 65.
Detailed power-down entry conditions are shown in Figures 48 through 55. The CKE
Truth Table, Table 11, is shown on page 66.
DDR2 SDRAMs require CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and
page 68. The number of clock cycles required to meet
whichever is greater.
Power-down mode (see Figure 47 on page 65) is entered when CKE is registered LOW
coincident with a NOP or DESELECT command. CKE is not allowed to go LOW during a
mode register or extended mode register command time, or while a READ or WRITE
operation is in progress. If power-down occurs when all banks are idle, this mode is
referred to as precharge power-down. If power-down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deacti-
vates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same
voltage as when it entered power-down; however, the clock frequency is allowed to
change. See “Precharge Power-Down Clock Frequency Change” on page 71.
The maximum duration for either active or precharge power-down is limited by the
refresh requirements of the device
entry and exit is limited by the
LOW, a stable clock signal, and stable power supply signals must be maintained at the
inputs of the DDR2 SDRAM, while all other input signals are “Don’t Care” except ODT.
Detailed ODT timing diagrams for different power-down modes are shown in Figures 58
through 65.
The power-down state is synchronously exited when CKE is registered HIGH (in
conjunction with an NOP or DESELECT command), as shown in Figure 47 on page 65.
t
WR or
64
t
CKE (MIN) parameter. While in power-down mode, CKE
t
WTR are satisfied, as shown in Figures 50 and 51 on
t
RFC (MAX). The minimum duration for power-down
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2Gb: x4, x8, x16 DDR2 SDRAM
t
WTR is either two or
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Power-Down Mode
t
WTR/
t
CK,