mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 22

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 4:
Operating Mode
DLL RESET
Write Recovery
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
Burst Definition
The normal operating mode is selected by issuing a command with bit M7 set to “0,” and
all other bits set to the desired values, as shown in Figure 9 on page 21. When bit M7 is
“1,” no other bits of the mode register are programmed. Programming bit M7 to “1”
places the DDR2 SDRAM into a test mode that is only used by the manufacturer and
should not be used. No operation or functionality is guaranteed if M7 bit is “1.”
DLL RESET is defined by bit M8, as shown in Figure 9 on page 21. Programming bit M8
to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns
back to a value of “0” after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 9 on page 21.
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the
internal auto precharge operation by WR clocks (programmed in bits M9–M11) from the
last data burst. An example of WRITE with auto precharge is shown in Figure 41 on
page 57.
WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9–M11. The user
is required to program the value of WR, which is calculated by dividing
onds) by
WR [cycles] =
tion or incompatibility with future versions may result.
Burst Length
t
AC or
4
8
t
CK (in nanoseconds) and rounding up a noninteger value to the next integer;
t
DQSCK parameters.
t
WR [ns] /
Starting Column
(A2, A1, A0)
Address
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 1
0 0
0 1
1 0
t
CK [ns]. Reserved states should not be used as unknown opera-
22
Burst Type = Sequential
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
Order of Accesses Within a Burst
2Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Burst Type = Interleaved
©2006 Micron Technology, Inc. All rights reserved.
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
t
WR (in nanosec-