mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 61

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

SELF REFRESH Command
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down. When in the self refresh mode, the DDR2
SDRAM retains data without external clocking. All power supply inputs (including V
must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-
tion.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering self refresh and is automatically
enabled upon exiting self refresh (200 clock cycles must then occur before a READ
command can be issued). The differential clock should remain stable and meet
specifications at least 1 x
input signals except CKE are “Don’t Care” during self refresh.
The procedure for exiting self refresh requires a sequence of commands. First, the differ-
ential clock must be stable and meet
going back HIGH. Once CKE is HIGH (
registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for
t
simple algorithm for meeting both refresh and DLL requirements is to apply NOP or
DESELECT commands for 200 clock cycles before applying any other command.
XSNR because time is required for the completion of any internal refresh in progress. A
t
CK after entering self refresh mode. All command and address
61
t
CK specifications at least 1 x
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CKE [MIN] has been satisfied with four clock
2Gb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH Command
©2006 Micron Technology, Inc. All rights reserved.
t
CK prior to CKE
t
CKE
REF
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