mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 56

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mt47h128m16hg-3-it

Manufacturer Part Number
mt47h128m16hg-3-it
Description
2gb X4, X8, X16 Ddr2 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
Figure 40:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
BA0, BA1, BA2
COMMAND 5
DQS, DQS#
ADDRESS
DQ 1
CK#
CKE
A10
DM
CK
NOP 6
Bank Write – without Auto Precharge
T0
Notes:
Bank x
ACT
RA
RA
T1
1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. BL = 4, AL = 0, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
7.
8.
9. Subsequent rising DQS signals must align to the clock within
t CK
times.
t
t
DSH is applicable during
DSS is applicable during
t RCD
t RAS
NOP 6
T2
t CH
t CL
WRITE 2
Bank x
Col n
3
T3
WL ± t DQSS (NOM)
WL = 2
t
t
DQSS (MAX) and is referenced from CK T6 or T7.
DQSS (MIN) and is referenced from CK T5 or T6.
NOP 6
T4
56
t WPRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP 6
T5
DI
n
T5n
t DQSL t DQSH t WPST
2Gb: x4, x8, x16 DDR2 SDRAM
NOP 6
9
T6
T6n
DON’T CARE
t
NOP 6
DQSS.
T7
©2006 Micron Technology, Inc. All rights reserved.
WRITE Command
t WR
NOP 6
TRANSITIONING DATA
T8
ALL BANKS
ONE BANK
Bank x 4
PRE
T9
t RP

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