mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 54

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 38:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
COMMAND
DQS, DQS#
DQS, DQS#
DQS, DQS#
ADDRESS
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE
Bank a,
Col b
T0
WRITE-to-READ
Notes:
WL - t DQSS
WL ± t DQSS
WL + t DQSS
NOP
T1
1. DI b = data-in for column b; D
2. BL = 4, AL = 0, CL = 3; thus, WL = 2.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. The number of clock cycles required to meet
7.
8. Subsequent rising DQS signals must align to the clock within
t
greater.
t
between module ranks.
WTR is referenced from the first positive CK edge after the last data-in pair.
WTR is required for any READ following a WRITE to the same device, but it is not required
DI
b
NOP
T2
DI
b
DI
b
T2n
8
NOP
T3
8
8
T3n
DON’T CARE
NOP
T4
54
OUT
n = data-out from column n.
TRANSITIONING DATA
t WTR 7
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WTR is either 2 or
2Gb: x4, x8, x16 DDR2 SDRAM
Bank a,
READ
T6
Col n
CL = 3
CL = 3
CL = 3
T7
NOP
t
DQSS.
©2006 Micron Technology, Inc. All rights reserved.
t
WTR/
WRITE Command
T8
t
NOP
CK, whichever is
T9
NOP
D
D
D
IN
IN
IN
T9n