mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 52
mt47h128m16hg-3-it
Manufacturer Part Number
mt47h128m16hg-3-it
Description
2gb X4, X8, X16 Ddr2 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT47H128M16HG-3-IT.pdf
(127 pages)
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Figure 34:
Figure 35:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
Consecutive WRITE-to-WRITE
Nonconsecutive WRITE-to-WRITE
Notes:
Notes:
t
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
3. Three subsequent elements of data-in are applied in the programmed order following
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within
t
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
3. Three subsequent elements of data-in are applied in the programmed order following
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within
DQSS (NOM)
DQSS (NOM)
COMMAND
DQS, DQS#
COMMAND
DQS, DQS#
ADDRESS
DI b.
DI n.
DI b.
DI n.
ADDRESS
CK#
DM
DQ
CK
CK#
DM
DQ
CK
WRITE
Bank,
Col b
WRITE
T0
Bank,
Col b
T0
WL ±
t
WL = 2
CCD
NOP
WL = 2
T1
NOP
T1
t
DQSS
WL ± t DQSS
T1n
52
WRITE
Bank,
Col n
T2
DI
b
NOP
T2
DI
b
T2n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2n
WL = 2
NOP
WRITE
6
Bank,
T3
Col n
6
T3
DON’T CARE
DON’T CARE
2Gb: x4, x8, x16 DDR2 SDRAM
T3n
T3n
WL = 2
NOP
6
T4
DI
NOP
n
T4
TRANSITIONING DATA
TRANSITIONING DATA
T4n
T4n
t
t
DQSS.
DQSS.
©2006 Micron Technology, Inc. All rights reserved.
NOP
6
6
T5
T5
NOP
DI
n
WRITE Command
T5n
T5n
NOP
NOP
6
T6
T6
T6n
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